Background

I designed a test platform for evaluating the floating gate fet performance of Aspinity’s AML100 chip. There were three main challenges for this platform:

1. The platform needed to withstand temperature cycling in an oven (used to “degrade” the chip)
2. The platform needed to be relatively cheap (hi-temp connectors tend to be cost prohibitive)
3. The platform needed to allow for swapping test devices (see #2, hi-temp IC test sockets are expensive)

I was able to spec low-cost DDR3 RAM connectors that were specced up to 150C; I designed the platform around the RAM connectors. The platform consisted of a main host board with circuits for conditioning signals as well as headers used to inject signals and carrier boards comprised of the device under test and circuits for telemetry.